1. Field of Invention
The present invention generally relates to a method for fabricating a dynamic random access memory (DRAM), and more particularly to a method for fabricating interconnects of a DRAM.
2. Description of Related Art
Dynamic random access memory (DRAM) is a widely used integrated circuit device, which plays an indispensable role in the electronic industry. FIGS. 1A and 1B are diagrammatic cross-sectional views showing successive stages of a conventional method for fabricating interconnects of a DRAM cell. With reference first to FIG. 1A, a semiconductor substrate 10 is provided, in which a plurality of insulating structures 20, for example, shallow trench isolation structures, are formed to isolate active areas. A plurality of transistor gates are subsequently formed on the substrate, which consist of a first doped polysilicon layer 30 and a tungsten silicide layer 40. A silicon nitride layer 50 and a spacer 60 surrounding the gate are successively formed for every transistor. Also, a bit line consisting of a second doped polysilicon layer 210 and a tungsten silicide layer 220 are formed to contact a source/drain region. A first insulating layer 230 is deposited and patterned to form an opening 240 to expose the source/drain region on the substrate.
With reference to FIG. 1B, a third doped polysilicon layer 250 is formed on the substrate, covering and filling the opening 240. The third doped polysilicon layer is then patterned to form a lower electrode 250 of a capacitor. After that, a hemispherical grain (HSG) layer 260 is formed on the surface of the lower electrode 250 to increase the surface coverage for the capacitor, and consequently the charging capacity. A capacitive dielectric layer (not shown), for example, a multi-layer structure of oxide/nitride/oxide (ONO), is formed on the surface of the HSG layer 260. The capacitive dielectric layer is formed by growing a thin oxide layer on the rough surface of the third doped polysilicon layer. Subsequently, a thin silicon nitride layer is deposited on the silicon oxide layer by using a chemical vapor deposition (CVD) method. Finally, a thermal oxidation process is performed to oxidize the surface of the silicon nitride layer to form the ONO structure. Subsequently, a fourth doped polysilicon layer is deposited and patterned to form an upper electrode 270 of the capacitor. Finally, a second insulating layer 280 is deposited on the substrate.
FIG. 2 is a diagrammatic cross-sectional view of a peripheral circuit of a DRAM showing a conventional method for fabricating interconnects. Note that the fabrication of a DRAM cell and the peripheral circuit of the DRAM are simultaneously performed. That is, a semiconductor substrate 10 is first provided, on which a plurality of transistor gates are formed, which consist of a first doped polysilicon layer 30 and a tungsten silicide layer 40. A silicon nitride layer 50 on the transistor gate and a spacer 60 surrounding the transistor gate are subsequently formed. A first insulating layer 230 and a second insulating layer 280 are successively deposited and patterned to form a plurality of contact windows. Finally, the contact windows are filled with tungsten to form interconnects 300. Unfortunately, problems arise when filling the contact windows with a metal barrier material or tungsten because of a higher aspect ratio of the contact windows.
Conventional methods for fabricating interconnects of a DRAM generally form contact windows required by the peripheral circuits at the last stage. Since the contact windows for forming interconnects generally have a small cross section and great depth, the fabricating complexities therefore increase as the aspect ratio of the contact windows increases, which implies an inferior production efficiency. Particularly, node contact windows are generally fabricated with a small opening according to the design rules, which typically require a taper etching to perform this task. The taper etching, however, creates a problem of having a higher resistance for the node contact window. A higher step height of the contact window also creates problems for filling a metal barrier material, for example, titanium/titanium nitride (Ti/Tin), into the contact windows. In addition, the higher aspect ratio of a deep trench also makes it very difficult to fill tungsten into the contact window, resulting in a higher resistance value for the contact windows.
In addition, bit line interconnects are conventionally fabricated using polysilicon. Since the resistance of the bit line interconnects using polysilicon is higher than that using tungsten, a higher power dissipation and a slow operating speed will occur.